tailieunhanh - An Experimental Approach to CDMA and Interference Mitigation phần 7

Sau khi chương trước người đọc nên có khá rõ ràng trong tâm trí của họ các giải pháp kiến trúc chính của các vấn đề phát hiện tín hiệu khác nhau mà đã được nêu bật. Câu hỏi hiện nay là làm thế nào để dịch nó vào thiết kế phần cứng tốt. | 3. Design of an All Digital CDMA Receiver 157 Figure 3-60. Influence of AFCU and CPRU on EC-BAID BT performance. Figure 3-61. Comparison between FP front end and BT front end L 64 . This page intentionally left blank Chapter 4 FROM SYSTEM DESIGN TO HARDWARE PROTOTYPING After the previous chapter the reader should have quite clear in their mind the main architectural solutions of the different signal detection issues which were highlighted. The question now is how to translate it into good hardware design. Introduced by a brief discussion about the main issues in design and implementation of wireless telecommunication terminals design flows design metrics design space exploration finite arithmetic effects rapid prototyping etc. this Chapter presents in detail the FPGA hardware implementation of the CDMA receiver described in Chapter 3. 1. VLSI DESIGN AND IMPLEMENTATION OF WIRELESS COMMUNICATION TERMINALS AN OVERVIEW As discussed in Chapter 1 the only viable solution for handling both the exponentially increasing algorithmic complexity of the physical layer and the battery power constraint in wireless terminals is to rely on a heterogeneous architecture which optimally explores the flexibility-powerperformance-cost design space. In this respect Figure 1-14 in Chapter 1 shows a typical heterogeneous System on a Chip SoC architecture employing several programmable processors either standard and application specific on chip memories bus based architectures dedicated hardware coprocessors peripherals and I O channels. The current trend in the design of digital terminals for wireless communications consists in moving from .