tailieunhanh - Digital logic testing and simulation phần 4

Nếu 1 được giao, sau đó một trong những yếu tố đầu vào phải được thiết lập là 0. Tuy nhiên, tín hiệu linh hoạt khác vẫn có thể được khởi tạo. Nói chung, khi một đầu vào phải được thiết lập để một giá trị để kiểm soát Ví dụ, một 0 trên một đầu vào một, hoặc NAND cửa thường là thích hợp hơn để lựa chọn đầu vào đó là đơn giản nhất để kiểm soát. | THE SUBSCRIPTED D-ALGORITHM 187 resolved by assigning a fixed binary value to the output of gate 8. If a 1 is assigned then one of the inputs must be set to 0. However the other flexible signal can still be instantiated. Generally when an input must be set to a controlling value for example a 0 on an input to an AND or NAND gate it is usually preferable to choose the input that is easiest to control. However in the present case an additional criterion may exist. If a fault on one of the two inputs to gate 14 has already been detected then the flexible signal D1 or D2 corresponding to the undetected input fault can be favored when a choice must be made. When D1 and D2 converge at the output of gate 8 if it is found that the upper input to gate 14 has already been tested then D1 can be purged by assigning a 0 to the upper input of gate 8. When a conflict occurs its resolution usually requires that segments of D chains be deleted. AALG accomplishes this with functions called DROPIT and DROPIT purges a chain segment when the end closest to the primary inputs is known. It works forward toward the gate under test. It must examine fanouts as it progresses so if two converging paths both have flexible signals then both chain segments must be deleted. When a flexible signal is deleted it may be replaced by a fixed binary signal. This signal when assigned to the input of a gate may be a controlling value for that gate and thus implies a logic value on the output. In that case the output must be further traced to the input of the gate s in its fanout to determine whether this output value is a controlling value at the input of the gate in its fanout. When D0 was assigned to the output of gate 14 a conflict occurred at gate 8 so a 1 was assigned to its output which required a 0 on one of its inputs. Primary input 6 was chosen. This required that the D2 chain from . 6 to the input of gate 14 be purged. A 0 on . 6 implies a 0 on the output of gate 12 so the .