tailieunhanh - PRINCIPLES OF COMPUTER ARCHITECTURE phần 6

Vẽ mạch cho một bộ giải mã 4-to-16 cây, sử dụng tối đa một fan hâm mộ và fan hâm mộ của hai. Một bản đồ hóa trực tiếp bao gồm 128 khe cắm. Bộ nhớ chính có 16K khối 16 từ. Thời gian truy cập bộ nhớ cache là 10 ns, và thời gian cần thiết để điền vào một khe cắm bộ nhớ cache là 200 ns. | CHAPTER 7 MEMORY 307 Draw the circuit for a 4-to-16 tree decoder using a maximum fan-in and fan-out of two. A direct mapped cache consists of 128 slots. Main memory contains 16K blocks of 16 words each. Access time of the cache is 10 ns and the time required to fill a cache slot is 200 ns. Load-through is not used that is when an accessed word is not found in the cache the entire block is brought into the cache and the word is then accessed through the cache. Initially the cache is empty. Note When referring to memory 1K 1024. a Show the format of the memory address. b Compute the hit ratio for a program that loops 10 times from locations 15 - 200. Note that although the memory is accessed twice during a miss once for the miss and once again to satisfy the reference a hit does not occur for this case. To a running program only a single memory reference is observed. c Compute the effective access time for this program. A fully associative mapped cache has 16 blocks with eight words per block. The size of main memory is 216 words and the cache is initially empty. Access time of the cache is 40 ns and the time required to transfer eight words between main memory and the cache is 1 gs. a Compute the sizes of the tag and word fields. b Compute the hit ratio for a program that executes from 20-45 then loops four times from 28-45 before halting. Assume that when there is a miss that the entire cache slot is filled in 1 gs and that the first word is not seen by the CPU until the entire slot is filled. That is assume load-through is not used. Initially the cache is empty. c Compute the effective access time for the program described in part b above. Compute the total number of bits of storage needed for the associative mapped cache shown in Figure 7-13 and the direct mapped cache shown in Figure 7-14. Include Valid Dirty and Tag bits in your count. Assume that the word size is eight bits. 308 CHAPTER 7 MEMORY a How far apart do memory references need to