tailieunhanh - PRINCIPLES OF COMPUTER ARCHITECTURE phần 5

Những xe buýt này cho phép hai toán hạng được lấy từ các tập tin đăng ký cùng một lúc, được điều hành bởi ALU, với các kết quả trả lại cho các tập tin đăng ký. các ALU Đơn vị kiểm soát lựa chọn đăng ký và chức năng ALU | 242 CHAPTER 6 DATAPATH AND CONTROL that we can include a time delay between inputs and outputs using the after keyword. In this case the event computing the value of F_OUT will be triggered 4 ns after a change in any of the input values. It is also possible to specify the architecture at a level closer to the hardware by specifying logic gates instead of logic equations. This is referred to as a structural model. Here is such a specification Structural model for the majority component In generating a structural model for the MAJORITY entity we will follow the gate design given in Figure 6-25b. We begin the model by describing a collection of logic operators in a special construct of VHDL known as a package. The package is assumed to be stored in a working library called WORK. Following the package specification we repeat the entity declaration and then using the package and entity declarations we specify the internal workings of the majority component by specifying the architecture at a structural level -- Package declaration in library WORK package LOGIC_GATES is Component AND3 port A B C in BIT X out BIT end component component OR4 port A B C D in BIT X out BIT end component component NOT1 port A in BIT X out BIT end component -- Interface entity MAJORITY is port A_IN B_IN C_IN in BIT F_OUT out BIT end MAJORITY -- Body -- Uses components declared in package LOGIC_GATES -- in the WORK library -- import all the components in use architecture LOGIC_SPEC of MAJORITY is -- declare signals used internally in MAJORITY signal A_BAR B_BAR C_BAR I1 I2 I3 I4 BIT begin -- connect the logic gates NOT_1 NOT1 port map A_IN A_BAR NOT_2 NOT1 port map B_IN B_BAR NOT_3 NOT1 port map C_IN C_BAR CHAPTER 6 DATAPATH AND CONTROL 243 AND_1 AND3 port map A_BAR b_in c_in I1 AND_2 AND3 port map a_in B_BAR C_IN I2 AND_3 AND3 port map a_in B_IN C_BAR 13 AND_4 AND3 port map a_in B_IN C_IN I4 OR_1 OR3 port map I1 I2 end LOGIC SPEC I3 I4 F_OuT The package .