tailieunhanh - computer organization and architecture p5

Các vấn đề thiết kế o Làm thế nào để xác định CPU thiết bị ban hành gián đoạn? § Nhiều dòng ngắt § giải pháp đơn giản nhất § không thực tế để dành nhiều dòng § nhiều I / O có khả năng gắn liền với mỗi dòng § một trong 3 kỹ thuật khác phải được sử dụng trên mỗi dòng | 41 Design issues o How does the CPU determine which device issued the interrupt Multiple Interrupt Lines most straightforward solution impractical to dedicate many lines multiple I O modules are likely attached to each line one of other 3 techniques must be used on each line Software Poll interrupt service routine polls each device to see which caused the interrupt using a separate command line on the system bus TESTI O raise TESTI O place I O module address on address lines check for affirmative response each I O module contains an addressable status register which CPU reads time consuming Daisy Chain hardware poll vectored interrupt occurs on interrupt request line which is shared by all I O modules CPU senses interrupt CPU sends interrupt acknowledge which is daisy-chained through all I O modules When it gets to requesting module it places its vector either an I O address or an ID which the CPU uses as a pointer to the appropriate device-service routine on the data lines No general interrupt-service routine needed still need specific ones Bus Arbitration vectored Universidade do Minho - Dep. Informatica - Campus de Gualtar - 4710-057 Braga - PORTUGAL- http William Stallings Computer Organization and Architecture 5th Ed. 2000 42 requires an I O module to first gain control of the bus before it can interrupt thus only one module can interrupt at a time when CPU detects the interrupt it ACK s requesting module then places its vector on the data lines another type of vectored interrupt If multiple interrupts have occurred how does the CPU decide which one to process o Multiple lines - assign priorities to lines and pick the one with highest priority o Software polling - order in which modules are polled determines priority o Daisy chain - order of modules on chain determines priority o Bus arbitration can employ a priority scheme through the arbiter or arbitration algorithm Direct Memory Access Drawbacks of Programmed and Interrupt-Driven I O o