tailieunhanh - Micro Electronic and Mechanical Systems 2009 Part 12

Tham khảo tài liệu 'micro electronic and mechanical systems 2009 part 12', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 376 Micro Electronic and Mechanical Systems 4. Modelling the D A interface For modelling of the D A interface the output circuit of the digital part is to be represented by a circuit that is supposed to drive an analog load. Note that mixed-mode simulation is considered. This means that an event scheduler is active marking the controlling input of the digital circuit Litovski Zwolinski 1997b . The event scheduler does not allow for two inputs to be active simultaneously because that is considered as a hazard. Hence modelling the output of an inverter is general enough for verification of the modelling procedure. Fig. 12. a Simple D A conversion circuit b Current generator waveform tru stands for the rising edge while trf for the falling edge duration of the transition Modelling of the D A interface is more complex problem than modelling of the A D interface because we need to generate voltage waveform that excites the analog part of the circuit out of a set of logic states. Conversion algorithms are mostly based on synthesis of an electronic circuit that replaces the logic element s output and is connected as an excitation to the particular node. Logic gate s delays also need to be considered and extracted by the event scheduler. The simplest solution of the D A conversion is illustrated in Fig. 12. Zwolinski et al. 1989 . There is a branch consisting of a constant conductance Go and current generator I and it is applied to D A node. The delay time is denoted by t0. Ratios I1 Go and Io Go correspond to levels of logic 1 and logic 0 respectively and different transition times from logic 1 to o and vice-versa are permitted. Current waveforms for transitions from logic 1 to o and vice-versa are given in Fig. 12b. A more complex output circuit is shown in Fig. 13. Arnout De Man 1978 . There are two voltage generators Eo Ro and E1 R1 applied to the analog node depending on logic element s output state. This function is realized by a switch controlled by Boolean .