tailieunhanh - Micro Electronic and Mechanical Systems 2009 Part 8

Tham khảo tài liệu 'micro electronic and mechanical systems 2009 part 8', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 236 Micro Electronic and Mechanical Systems shallow trench isolation STI approach. A gate insulator of Si dioxide SiO2 is thermally growth and a polycrystalline-Si poly-Si layer as a gate electrode deposited by using the chemical vapor deposition CVD process is then formed. In order to form a n-S D scheme the layer of SiN as hard mask is deposited by CVD. After the patterning of the gate stack see Fig. 2 a a SiN layer for forming the spacer is deposited and etched back as shown in Fig. 2 b . The sidewall spacer hard mask is used for etching Si and BOX respectively see Fig. 2 c . A layer of poly-Si is deposited as SDT shown in Fig. 2 d . After the deposition and planarization of the SiO2 layer the etching process is performed in order to form a BOX layer under the source and drain regions see Fig. 2 e . The poly-Si layer is deposited patterned and etched to create the active region of the S D as shown in Fig. 2 f . Next the S D implantation process is carried out by arsenic As 10 KeV 1014 cm-2. Rapid thermal annealing RTA process is followed to activate the dopants and repair the lattice damage that is caused by the implantation process. Finally a conventional SOI fabrication flow can be used for back-end-of-line BEOL processing. The simulation parameters are Tbox 40 nm Tboi 50 nm Ts d Tsi 5 nm and Tgox nm for the n-S D. Various gate lengts LG LCH - 9 nm of 10 nm 70 nm were investiaged. Notice that all the parameters of the UTSOI NMOS are equivalent to those of the n-S D NMOS expect that the Tbox is equal to the Tboi 50 nm . Fig. 1. Schematic cross-sectional view of an n-channel SA-nFET. Note that the LSDT and LSP are two important pa ra meters of the SA-nFET. a Self-Aligned n-Shaped Source Drain Ultrathin SOI MOSFETs 237 b SiN spacer poly-Si GOX p Si BOX p substrate c d e 238 Micro Electronic and Mechanical Systems f Fig. 2. The SA-nFET fabrication process 1 2 a gate patterning b SiN spacer formation c Si BOX etch with a SiN mask d poly-Si deposition e .