tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P30

High Level Synthesis: from Algorithm to Digital Circuit- P30: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 280 . Molina et al. synthesized. Indeed our algorithm becomes the best choice for non heterogeneous specifications where the latency number of operations and data dependencies prevent reaching homogeneous distributions of operations among cycles. The areas of conventional implementations synthesized from non heterogeneous specifications may be slightly smaller than ours but only where conventional algorithms are able to find nearly homogeneous distributions of the number of operations of every different type and width executed per cycle and for a similar reason as for heterogeneous specifications. The implementations obtained synthesizing non heterogeneous specifications satisfy the following features The amount of cycle length saved increases in inverse ratio to the latency. As latency decreases the number of chained operations that have to be executed in a cycle grows as well as the potential benefit from distributing over several cycles the execution of certain operations. The amount of area saved increases in direct proportion to the circuit latency. As the number of cycles grows more uniform distributions in the computational costs of operations may be found among them by our algorithm. In order to illustrate the effectiveness of our method with non heterogeneous specifications we have synthesized the fifth order elliptic wave filter formed by 34 unsigned operations 26 additions and 8 multiplications . In this specification all variables input and output ports are 16 bits wide. The implementations obtained have been compared to the ones produced by BC. Table shows the area and cycle length of the implementations obtained for three different latencies 8 11 and 16 cycles. Our algorithm saves up to 36 of cycle length and 27 of area for 8 and 16 clock cycles respectively. Further Applications of the Proposed Techniques The proposed design techniques have been implemented in HLS algorithms. However they can also be applied before or after the synthesis