tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P18

High Level Synthesis: from Algorithm to Digital Circuit- P18: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 158 P. Coussy et al. Fig. Operator area vs. sizing approaches 9 9 8 9 9 4 Max 8 4 3 9 Max in1 in2 Boston n 40 slices 34 slices 24 slices a b c Storage Element Optimization Because currently there is no feed-back loop in the design flow the registers optimization has to be done during the conception of the processing unit. The choice of the location of an unconstrained variable user can define the location of variables in a register or in a memory has to be done according to the minimization of two contradictory cost criteria The cost of a register is higher than the cost of a memory point. The cost to access data in a register is lower than the cost to access data in memory because of the necessity to compute the address . Two criteria are used to choose the memorization location of the data A variable whose life time is inferior to a locality threshold is stored in a register. The location of memorization depends on the class of the variable. Data are classified into three categories Temporary processing data declared or undeclared . Constant data read-only . Ageing data which serves to express the recursivity of the algorithm to be synthesized via their assignment after having been utilized . The optimal storage of a given data element depends upon its declaration and its life time. It can be either stored in a memory bank of the MEMU or in a storage element of the processing unit PU. The remaining difficulty lies in selecting an optimal locality threshold which results in minimizing the cost of the storage unit. The synthesis tool leaves the choice of the value of the locality threshold up to the user. In order to help the designer GAUT proposes a histogram of the life time of the variables normalized by the utilization frequency which is calculated from the scheduled DFG. The architecture of the processing unit is composed of a processing part and a memory part . memory plan and the associated control state machine FSM Fig. . The memory part