tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P17

High Level Synthesis: from Algorithm to Digital Circuit- P17: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 148 P. Coussy et al. RTL. Designers will spend more time exploring the design space with multiple what if scenarios. They will obtain a range of implementation alternatives from which they will select the architecture providing the best power speed gate count trade-off. This chapter presents GAUT which is an open-source HLS tool dedicated to DSP applications 1 . Starting from an algorithmic bit-accurate specification written in C C a throughput constraint Initiation Interval and a clock period the tool extracts the potential parallelism before processing the selection the allocation the scheduling and the binding tasks. GAUT generates a potentially pipelined architecture composed of a processing unit a memory unit and a communication unit. Several RTL VHDL models for the logic synthesis and SystemC CABA Cycle Accurate Bit Accurate and TLM-T Transaction Level Model with Timing are automatically generated with their respective test benches. The chapter is organized as follow Sect. introduces our design flow and presents the targeted architecture. Section details each step of our high-level synthesis flow. In Sect. experimental results are provided. Overview of the Design Environment High-level synthesis enables the semi automatic search for architectural solutions that respect the specified constraints while optimizing the design objectives. To be efficient the synthesis must rely on a design method which takes into account the specificity of the application fields. We have focused on the domain of real-time digital signal processing and we have formalized a dedicated design approach for this type of application where the regular and periodic data-intensive computations dominate. GAUT 1 takes as input a C description of the algorithm that has to be synthesized. The mandatory constraints are the throughput specified through an initiation interval which represents the constant interval between the start of successive iterations and the clock period. .