tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P14

High Level Synthesis: from Algorithm to Digital Circuit- P14: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 7 All-in-C Behavioral Synthesis and Verification with CyberWorkBench 117 Wire delays of global wires between modules need to be analyzed carefully since those delays can be significant when the connected modules are placed far away. Our RTL FloorPlanner 3 takes the RTL modules generated by the behavioral synthesizer. Accurate timing information is extracted from the floorplanner and fed back to the behavioral synthesizer. The behavioral synthesizer reads the timing information and re-schedules the C code considering the timing information. Verification Flow The functionality of the hardware described in C can be verified at the behavioral level while performance and timing are verified at the cycle-accurate level or RTL through simulation. Debugging the generated RTL is however not an easy task since C variables are shared in a register and various optimizations are applied. We therefore provide a behavioral C source code debugger linked to our cycle-accurate simulation and FPGA emulation tool. After verifying each hardware module the entire SoC is simulated in order to analyze the performance and or to find inter-modules problems such as low performance through bus collision or inconsistent bit orders between modules. Since such entire chip performance simulation is extremely slow in RTL-based HW-SW co-simulation CWB generates cycle accurate C simulation models which can run up to hundred times faster than RTL models. Our HW-SW co-simulator 3 uses the generated cycle-accurate model for this purpose. The simulator allows designers to simulate and debug both hardware and software at the C source code level at the same time. If any performance problems are found designers can change the hardware-software partitioning or algorithm directly at the C level and can then repeat the entire chip simulation. This flow implies a much smaller and therefore faster re-design cycle than in a conventional RTL methodology. The C description is the only initial and final SoC