tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P8

High Level Synthesis: from Algorithm to Digital Circuit- P8: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 56 S. Aditya and V. Kathail the high degree of chip integration made possible by Moore s law. For example a cell-phone chip now contains multiple modems imaging pipeline for a camera video codecs music players etc. A video codec used to be a whole chip a few years back and now it is a small part of the chip. Second there is relentless pressure to reduce time-to-market and lower prices. It is clear that automation is the key to success. Automatic application engine synthesis AES from a high level algorithmic description significantly reduces both design time and design cost. There is a growing consensus in the design community that hardware software co-design high level synthesis and high level IP reuse are together necessary to close the design productivity gap. Application Engine Design Space Application engines like multi-standard video codecs are large complex systems containing a significant number of processing blocks with complex dataflow and control flow among them. Externally these engines interact with system CPU system bus and other application engines. The ability to synthesize complex application engines from C algorithms automatically requires a careful examination of the type of architectures that lend themselves well to such automation techniques. Broadly speaking there are three main approaches for designing application engines 4 see Fig. . 1. Dedicated hardware accelerators They provide the highest performance and the lowest power. Typically they are 2-3 orders of magnitude better in power and performance than a general purpose processor. They are non-programmable but can provide limited amount of multi-modal execution based on configuration parameters. There are two approaches for automatic synthesis of dedicated hardware blocks Customizable or Configurable Processors Architectural F Synthesis of Accelerators FPGAs Behavioral Synthesis of Accelerators FPGAs Hybrid Application Engines Fig. The application engine design space 4 .