tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P5

High Level Synthesis: from Algorithm to Digital Circuit- P5: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 26 R. Gupta and F. Brewer Conclusions This brief retrospective is more than anything else a personal perspective. This is not just a caveat against inevitable omissions of important work in the area but also an expression of humility for a large number of significant contributions that have continually enabled newer generations of researchers to see farther than their predecessors. Looking back activity in HLS is marked by an early period of intense activity in synthesis in the eighties its drop off divergence from algorithmic optimizations and a subsequent reemergence as primarily a modeling and architectural specification challenge. Among some of the most exciting developments in the recent years are contributions from computer architecture researchers in defining modeling schemes that rely more on operation-centric behaviors and its early commercialization as BlueSpec. While it is too early to tell how HLS will emerge through these efforts even when it is not called HLS per se it is clear that the design decisions that affect code transformations such as transformations of loops and conditionals and architectural design such as pipeline structures are paramount to a successful synthesis solution. In other words the early attempts at optimization from algorithmic descriptions were somewhat premature and naive in expectation of a quick success modeled along the lines of logic synthesis. Indeed a shift in design tools and methods does not happen in isolation from the practitioners who must use these tools. Just as logic synthesis enabled RTL designers to try their hands at what used to be primarily a circuit design activity the future adoption of HLS will involve enabling a new class of practitioners to do things they can not do now. Today we have broad categories of pain-points in this area architects have to deal with too many design knobs that need to be turned to produce a design that is cost perfor-mance competitive in silicon whereas ASIC implementers .