tailieunhanh - High Level Synthesis: from Algorithm to Digital Circuit- P3

High Level Synthesis: from Algorithm to Digital Circuit- P3: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 6 P. Urard et al. Low Power LDPC Encoder 240Mhz vs 120Mhz 3 block size 4 code rates 12 modes Synthesis time 5mn Specs met same as manual implementation Specs met same throughput BUT with half clock frequency T1 L1 E time 3. 0 Sequential Specs not met Fig- 1-7 HLS architecture explorations Example FFT butterfly radix2 radix4 X - . ------ S0 X S2 UwJ X2 X. S1 X S3 VwaZ V wy Radix2 4 multipliers Radix4 Xo Xi X2 X3 So S1 S2 S3 Fig. Medium term need arithmetic optimizations 3 multipliers allow the designer to keep a high level of abstraction and to focus on functionality. For sure this would have to be based on some pre-characterization of the HW. Now HLS is being deployed new needs are coming out for more automation and more optimization. Deep arithmetic reordering is one of those needs. The current generation of tools is effectively limited in terms of arithmetic reordering. As an example how to go from a radix2 FFT to a radix4 FFT without re-writing the algorithm Figure shows one direction new tools need to explore. Taylor Expansion Diagrams seems promising in this domain but up to now no industrial EDA tool has shown up. Finally after a few years spent in the C-level domain it appears that some of the most limiting factors to exploration as well as optimization are memory accesses. If designer chose to represent memory elements by RAMs instead of Dflip-flop then the memory access order needs to be explicit in the input C code as soon as this is not a trivial order. Moreover in case of partial unroll of some FOR loops dealing 1 User Needs 7 with data stored in a memory the access order has to be re-calculated and C-code has to be rewritten to get a functional design. This can be resumed to a problem of memory precedence optimization. The current generation of HLS tools have a very low level of exploration of memory precedence when they have some some tool simply ignore it creating non-functional designs In order to illustrate this problem let take an in-place

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