tailieunhanh - Adaptive Techniques for Dynamic Processor Optimization Theory and Practice Episode 2 Part 6

Tham khảo tài liệu 'adaptive techniques for dynamic processor optimization theory and practice episode 2 part 6', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | Chapter 11 Dynamic and Adaptive Techniques in SRAM Design 253 n_Bit n_arvdd downvdd n_ Bit n 1_Bit n 1arvdd n 1_ Bit 2nd Metal 4th Meta P-Tr n WE Nd- Capacitive Write Assist Circuit WE n I 1 I I I WE n 1 P-Tr n 1 N-Tr n 1 Figure Charge sharing for supply reduction 14 . 2007 IEEE Since extra supplies are not always available in product design another example 14 uses charge sharing to lower the supply to the columns being written to. As shown in Figure downvdd is precharged to VSS. For a write operation supplies to the selected columns are disconnected from VDD and shorted to downvdd . The charge sharing lowers the supply s voltage to a level determined by the ratio of the capacitances allowing writes to occur easily. 254 John J. Wuu Yet another example 21 uses a power-line-floating write technique to assist write operations. Instead of switching in a separate supply or charge sharing the supply as in previous examples the supply to the write columns is simply switched off floating the column supply lines at VDD Figure . As the cells are written to the floating supply line Vddm discharges through the 0 bitline as shown in Figure . The decreased supply voltage allows easy writing to the cells. As soon as the cell flips to its intended state the floating supply line s discharge path is cut off preventing the floating supply line from fully discharging Figure . a b Figure Power-line-floating write 21 . IEEE 2006 Chapter 11 Dynamic and Adaptive Techniques in SRAM Design 255 In all column voltage manipulation schemes nonselected cells must retain state with the lowered supply. Row Voltage Optimization Similar to the previous section designers can apply voltage manipulation in the row direction as well. However unlike column-based voltage optimization row-based voltage optimization generally cannot simultaneously optimize for both read and write margins in the same operation as needed in a column-multiplexed design. Therefore .

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