tailieunhanh - Báo cáo hóa học: " Research Article Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design | Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2011 Article ID 927670 11 pages doi 2011 927670 Research Article Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design Bertrand Le Gal1 and Emmanuel Casseau2 1IMS Laboratory UMR-CNRS 5218 Polytechnic Institute of Bordeaux IPB University of Bordeaux 33405 Talence CEDEX France 2IRISA-CAIRN laboratory ENSSAT Engineering School University of Rennes 1 BP 80518 22305 Lannion CEDEX France Correspondence should be addressed to Bertrand Le Gal Received 28 June 2010 Revised 21 October 2010 Accepted 19 January 2011 Academic Editor Juan A. Lopez Copyright 2011 B. Le Gal and E. Casseau. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. High-level synthesis HLS currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on uniform-width resources according to the worstcase data requirements that is the largest word length. HLS techniques have been reviewed for the last few years to benefit from multiple word-length fixed point description of the algorithms to be implemented. Aims were to save design area and power consumption. Unfortunately data-width timing issues over the operation s latency have not been taken into account accurately. In this paper an HLS process that takes care of the delay of the operators according to the data width is presented. Experimental results show that our approach achieves significant design latency saving or area decrease compared to a conventional synthesis. 1. Introduction Multimedia communications and more generally consumer electronics applications are witnessing a rapid development towards integrating a complex system on a chip .