tailieunhanh - Hardware Acceleration of EDA Algorithms- P6

Hardware Acceleration of EDA Algorithms- P6: Single-threaded software applications have ceased to see significant gains in performance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a significant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, field-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose singlethreaded CPU | 80 5 Accelerating Boolean Satisfiability on an FPGA The third term represents the number of bits required to record the index of the bin in which the variable was assigned or implied which requires as many bits as the logarithm of the number of bins log2 . c . Ag Device The total BRAMSIZE for the XC4VFX140 part is Mb. Solving the above equation using a maximum number of variables Vtot of 10K gives Ctot 280K clauses the capacity of the system. Chapter Summary In this chapter we have presented an FPGA-based approach for Boolean satisfiability in which the traversal of the implication graph as well as conflict clause generation is performed in hardware in parallel. In our approach clauses are stored in FPGA slices. In order to solve large SAT instances we heuristically partition the clauses into a number of bins each of which can fit in the FPGA. This is done in a preprocessing step. The entire instance is solved using both intra- and interbin non-chronological backtrack which is implemented in hardware. The on-chip BRAM is used for storing all the bins of a partitioned CNF problem. The embedded PowerPC processor on the FPGA performs the task of loading the appropriate bin from the BRAM as requested by the hardware. Our entire flow has been verified for correctness on a Virtex-II Pro based evaluation platform. We project the runtimes obtained on this platform to an industry-strength XC4VFX140-based system and show that a speedup of 17 x can be obtained over the best-in-class software approach. The projected system can handle instances with as many as 280K clauses on 10K variables. References 1. http cs research formalmethods minisat . The MiniSAT Page 2. Abramovici M. de Sousa J. Saab D. A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware. In Proceedings Design Automation Conference DAC pp. 684-690 1999 3. Cook S. The complexity of theorem-proving procedures. In Proceedings Third ACM Symposium