tailieunhanh - Hardware and Computer Organization- P7

Hardware and Computer Organization- P7:Today, we often take for granted the impressive array of computing machinery that surrounds us and helps us manage our daily lives. Because you are studying computer architecture and digital hardware, you no doubt have a good understanding of these machines, and you’ve probably written countless programs on your PCs and workstations. | Chapter 7 in the data corresponding to intentional gaps so as not to create regions of data containing nonaligned accesses. Also notice that when we are doing 32-bit word accesses address bits A0 and A1 aren t being used. This might prompt you to ask If we don t use them what good are they However we do need them when we need to access a particular byte within the 32-bit words. A0 and A1 are often called the byte selector address lines because that is their main function. Another point is that we really only need byte selectors when we are writing to memory. Reading from memory is fairly harmless but writing changes everything. Therefore you want to be sure that you modify only the byte you are interested in and not the others. From a hardware designer s perspective having byte selectors allows you to qualify the write operation to only the byte that you are interested in. Many processors will not explicitly have the byte selector address lines at all. Rather they provide signals on the status bus which are used to qualify the WRITE operations to memory. What about storing 16-bit quantities a short data type in 32-bit memory locations The same rules apply in this case. The only valid addresses would be those addresses divisible by 2 such as 000000 000002 000004 and so on. In the case of 16-bit word addressing the lowest order address bit A0 isn t needed. For our 68K processor which has a 16-bit wide data bus to memory we can store two bytes in each word of memory so A0 isn t used for word addressing and becomes the byte selector for the processor. Figure shows a typical 32-bit processor and memory system interface. The READ signal from the processor and the CHIP SELECT signals have been omitted for clarity. The processor has a 32-bit data bus and a 32-bit address bus. The memory chips represent one page of RAM somewhere in the address space of the processor. The exact page of memory would be determined by the design of the Address Decoder logic block. The RAM .