tailieunhanh - Sequential Verulog Topicspart 6

Sequential UDPs Sequential UDPs differ from combinational UDPs in their definition and behavior. Sequential UDPs have the following differences | Sequential UDPs Sequential UDPs differ from combinational UDPs in their definition and behavior. Sequential UDPs have the following differences The output of a sequential UDP is always declared as a reg. An initial statement can be used to initialize output of sequential UDPs. The format of a state table entry is slightly different. input1 input2 . inputN current_state next_state There are three sections in a state table entry inputs current state and next state. The three sections are separated by a colon symbol. The input specification of state table entries can be in terms of input levels or edge transitions. The current state is the current value of the output register. The next state is computed based on inputs and the current state. The next state becomes the new value of the output register. All possible combinations of inputs must be specified to avoid unknown output values. If a sequential UDP is sensitive to input levels it is called a level-sensitive sequential UDP. If a sequential UDP is sensitive to edge transitions on inputs it is called an edge-sensitive sequential UDP. Level-Sensitive Sequential UDPs Level-sensitive UDPs change state based on input levels. Latches are the most common example of level-sensitive UDPs. A simple latch with clear is shown in Figure 12-3. Figure 12-3. Level-Sensitive Latch with clear In the level-sensitive latch shown above if the clear input is 1 the output q is always 0. If clear is 0 q d when clock 1. If clock 0 q retains its value. The latch can be described as a UDP as shown in Example 12-7. Note that the dash - symbol is used to denote no change in the state of the latch. Example 12-7 Verilog Description of Level-Sensitive UDP Define level-sensitive latch by using UDP. primitive latch q d clock clear declarations output q reg q q declared as reg to create internal storage input d clock clear sequential UDP initialization only one initial statement allowed initial q 0 initialize output to value 0 state .