tailieunhanh - Design for Low Power

Introduction to CMOS VLSI Design Design for Low Power | Introduction to CMOS VLSI Design Design for Low Power Slide Design for Low Power Outline Power and Energy Dynamic Power Static Power Low Power Design Slide Design for Low Power Power and Energy Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power: Slide Design for Low Power Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T Slide Design for Low Power Dynamic Power Cont. Slide Design for Low Power Dynamic Power Cont. Slide Design for Low Power Activity Factor Suppose the system clock frequency = f Let fsw = af, where a = activity factor If the signal is a clock, a = 1 If the signal switches once per cycle, a = ½ Dynamic gates: Switch either 0 or 2 times per cycle, a = ½ Static gates: Depends on design, but typically a = Dynamic power: Slide Design for Low Power Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. Slide Design for Low Power Example 200 Mtransistor chip 20M logic transistors Average width: 12 l 180M memory transistors Average width: 4 l V 100 nm process Cg = 2 fF/mm Slide Design for Low Power Dynamic Example Static CMOS logic gates: activity factor = Memory arrays: activity factor = (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current. Slide Design for Low Power Dynamic Example Static CMOS logic gates: activity factor = Memory arrays: activity factor = (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance. Slide Design for Low . | Introduction to CMOS VLSI Design Design for Low Power Slide Design for Low Power Outline Power and Energy Dynamic Power Static Power Low Power Design Slide Design for Low Power Power and Energy Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power: Slide Design for Low Power Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T Slide Design for Low Power Dynamic Power Cont. Slide Design for Low Power Dynamic Power Cont. Slide Design for Low Power Activity Factor Suppose the system clock frequency = f Let fsw = af, where a = activity factor If the signal is a clock, a = 1 If the signal switches once per cycle, a = ½ Dynamic gates: Switch either 0 or 2 times per .