tailieunhanh - Digital systems testing and testable design P2

Tham khảo tài liệu 'digital systems testing and testable design p2', kỹ thuật - công nghệ, kĩ thuật viễn thông phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 14 MODELING Figure Canonical structure of a synchronous sequential circuit Figure Three types of flip-flops caused by a single input change to Ij until a stable configuration is reached denoted by the condition N qi Ij qh Such stable configurations are shown in boldface in the flow table. Figure shows a flow table for an asynchronous machine and Figure shows the canonical structure of an asynchronous sequential circuit. Functional Modeling at the Logic Level 15 x x2 00 01 11 10 1 1 0 5 1 2 0 1 0 2 1 0 2 0 2 0 5 1 3 3 1 2 0 4 0 3 0 4 3 1 5 1 4 0 4 0 5 3 1 5 1 4 0 5 1 Figure A flow table z combinational circuit Figure Canonical structure of an asynchronous sequential circuit For test generation a synchronous sequential circuit S can be modeled by a pseudocombinational iterative array as shown in Figure . This model is equivalent to the one given in Figure in the following sense. Each cell C z of the array is identical to the combinational circuit C of Figure . If an input sequence x 0 x l .x k is applied to S in initial state y 0 and generates the output sequence z 0 z l .z and state sequence y 1 y 2 .y k 1 then the iterative array will generate the output z z from cell i in response to the input x z to cell z 1 z k . Note that the first cell also receives the values corresponding to y 0 as inputs. In this transformation the clocked F Fs are modeled as combinational elements referred to as pseudo-F Fs. For a JK F F the inputs of the combinational model are the present state q and the excitation inputs J and K and the outputs are the next state q and the device outputs y and y. The present state q of the F Fs in cell z must be equal to the q output of the F Fs in cell z-1. The combinational element model corresponding to a JK F F is defined by the truth table in Figure a . Note that here q y. Figure b shows the general F F model. 16 MODELING Figure Combinational iterative array model of a synchronous sequential circuit q