tailieunhanh - ARM Architecture Reference Manual- P27

ARM Architecture Reference Manual- P27: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | Glossary Branch prediction Is where an ARM implementation chooses a future execution path to prefetch along see Prefetching . For example after a branch instruction the implementation can choose to prefetch either the instruction following the branch or the instruction at the branch target. Byte Is an 8-bit data item. Cache Is a block of high-speed memory locations whose addresses are changed automatically in response to which memory locations the processor is accessing and whose purpose is to increase the average speed of a memory access. Cache contention Is when the number of frequently-used memory cache lines that use a particular cache set exceeds the set-associativity of the cache. In this case main memory activity goes up and performance drops. Cache hit Is a memory access which can be processed at high speed because the data it addresses is already in the cache. Cache line Is the basic unit of storage in a cache. Its size is always a power of two usually 4 or 8 words and is required to be aligned to a suitable memory boundary. A memory cache line is a block of memory locations with the same size and alignment as a cache line. Memory cache lines are sometimes loosely just called cache lines. Cache line index Is a number associated with each cache line in a cache set. Within each cache set the cache lines are numbered from 0 to set associativity -1. Cache lockdown Alleviates the delays caused by accessing a cache in a worst-case situation. Cache lockdown allows critical code and data to be loaded into the cache so that the cache lines containing them are not subsequently re-allocated. This ensures that all subsequent accesses to the code and data concerned are cache hits and so complete quickly. Cache lockdown blocks Consist of one line from each cache set. Cache lockdown is performed in units of a cache lockdown block. Cache miss Is a memory access which cannot be processed at high speed because the data it addresses is not in the cache. Cache sets Are areas