tailieunhanh - ARM Architecture Reference Manual- P24

ARM Architecture Reference Manual- P24: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | VFP Instructions Notes Vectors Rounding When the LEN field of the FPSCR indicates scalar mode vector length 1 FMSCS performs just one multiply-subtract operation where vec_len 1 Sd 0 Sd Sn 0 Sn and Sm 0 Sm. When the LEN field indicates a vector mode vector length 1 FMSCS might perform more than one multiply-subtract operation. Addressing Mode 1 - Single-precision vectors non-monadic on page C5-2 shows how FMSCS encodes registers and determines vec_len Sd i Sn i and Sm i . The operation is a fully-rounded multiplication followed by a fully-rounded subtraction. The rounding mode is determined by the FPSCR. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. C4-63 VFP Instructions FMSR 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0 cond 1 1 1 0 0 0 0 0 Fn Rd 10 10 N SBZ 1 SBZ The FMSR Floating-point Move to Single-precision from Register instruction transfers the contents of the ARM register Rd to the single-precision register Fn. The value transferred can subsequently be treated either as an integer if used as the source register of a FSITOD FSITOS FUITOD or FUITOS instruction or as a single-precision floating-point number if used by other arithmetic instructions . Syntax FMSR cond Sn Rd where cond Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-5. If cond is omitted the AL always condition is used. Sn Is the destination register. Its number is encoded as Fn top 4 bits and N bottom bit . Rd Is the source ARM register. Architecture version All Exceptions None Operation if ConditionPassed cond then Sn Rd C4-64 Copyright 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E VFP Instructions Notes Conversions In the programmer s model FMSR does not perform any conversion on the value transferred. Both the source register Rd and the destination register Sn can contain either an integer or a single-precision floating-point number. Arithmetic instructions on .