tailieunhanh - ARM Architecture Reference Manual- P15

ARM Architecture Reference Manual- P15: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | The 26-bit Architectures 26-bit configuration 1. If PROG32 is not active the processor is locked into 26-bit modes that is cannot be placed into a 32-bit mode by any means and handles exceptions in 26-bit modes. This is called a 26-bit configuration. In this configuration CMNP CMPP TEQP and TSTP instructions or the MSR instruction can be used to switch to 26-bit modes. Attempts to write CPSR bits 4 2 M 4 2 are ignored stopping any attempts to switch to a 32-bit mode and SVC_26 mode is used to handle memory aborts and Undefined Instruction exceptions. The PC is limited to 24 bits limiting the addressable program memory to 64MB. 2. If PROG32 is not active DATA32 has the following actions If DATA32 is not active all data addresses are checked to ensure that they are between 0 and 64MB. If a data address is produced with a 1 in any of the top 6 bits an address exception is generated. If DATA32 is active full 32-bit addresses can be produced and are not checked for address exceptions. This allows 26-bit programs to access data in the full 32-bit address space. Vector exceptions When the processor is in a 32-bit configuration PROG32 is active and in a 26-bit mode CPSR 4 0 data access but not instruction fetches to the exception vectors address 0x0 to 0x1 F causes a data abort. This is known as a vector exception. Vector exceptions are always produced if the exception vectors are written in a 32-bit configuration and a 26-bit mode. It is IMPLEMENTATION DEFINED whether reading the exception vectors in a 32-bit configuration and a 26-bit mode also causes a vector exception. Vector exceptions are provided to support 26-bit backwards compatibility. When a vector exception is generated it indicates that a 26-bit mode process is trying to install a 26-bit vector handler. Because the processor is in a 32-bit configuration exceptions are handled in a 32-bit mode so a veneer must be used to change from the 32-bit exception mode to a 26-bit mode before calling the 26-bit .