tailieunhanh - ARM Architecture Reference Manual- P14

ARM Architecture Reference Manual- P14: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | Thumb Instructions Notes Data abort F or details of the effects of the instruction if a data abort occurs see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not word-aligned and no data abort occurs the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor see Chapter B2 The System Control Coprocessor and alignment checking is enabled an address with bits 1 0 0b00 causes an alignment exception a type of data abort . Equivalent ARM syntax and encoding STR Rd Rn immed_5 4 31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 210 1110 0 10 110 0 0 Rn Rd 0 0 0 0 0 immed_5 0 0 ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A7-87 Thumb Instructions STR 2 15 14 13 12 11 10 9 8 6 5 3 2 0 0 10 10 0 0 Rm Rn Rd This form of STR allows 32-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for pointer large offset arithmetic and for accessing a single element of an array. Syntax STR Rd Rn Rm where Rd Is the register that contains the word to be stored to memory. Rn Is the register containing the first value used in forming the memory address. Rm Is the register containing the second value used in forming the memory address. Architecture version All T variants Exceptions Data Abort Operation address Rn Rm if address 1 0 0b00 Memory address 4 Rd else Memory address 4 UNPREDICTABLE Notes Data abort For details of the effects of the instruction if a data abort occurs see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not word-aligned and no data abort occurs the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor see Chapter B2 The System Control Coprocessor and alignment checking is enabled an address with bits 1 0 0b00 causes an alignment exception a type of data abort . A7-88 Copyright 1996-2000 ARM Limited. All rights .