tailieunhanh - ARM Architecture Reference Manual- P10

ARM Architecture Reference Manual- P10: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | ARM Addressing Modes Table 5-1 shows the relationship for LDM instructions. Table 5-1 LDM addressing modes Non-stack addressing mode Stack addressing mode L bit P bit U bit LDMDA Decrement After LDMFA Full Ascending 1 0 0 LDMIA Increment After LDMFD Full Descending 1 0 1 LDMDB Decrement Before LDMEA Empty Ascending 1 1 0 LDMIB Increment Before LDMED Empty Descending 1 1 1 Table 5-2 shows the relationship for STM instructions. Table 5-2 STM addressing modes Non-stack addressing mode Stack addressing mode L bit P bit U bit STMDA Decrement After STMED Empty Descending 0 0 0 STMIA Increment After STMEA Empty Ascending 0 0 1 STMDB Decrement Before STMFD Full Descending 0 1 0 STMIB Increment Before STMFA Full Ascending 0 1 1 ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A5-55 ARM Addressing Modes Addressing Mode 5 - Load and Store Coprocessor There are four addressing modes which are used to calculate the address of a Load or Store Coprocessor instruction. The general instruction syntax is opcode cond L coproc CRd addressing_mode where addressing_mode is one of the following four options 1. Rn - offset_8 4 See Load and Store Coprocessor - Immediate offset on page A5-58. 2. Rn - offset_8 4 See Load and Store Coprocessor - Immediate pre-indexed on page A5-60. 3. Rn - offset_8 4 See Load and Store Coprocessor - Immediate post-indexed on page A5-62. 4. Rn option See Load and Store Coprocessor - Unindexed on page A5-64. Encoding The following diagram shows the encoding for this addressing mode 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W L Rn CRd cp offset_8 The P bit Has two meanings P 1 Indicates the use ofpost-indexed addressing or unindexed addressing the W bit determines which . The base register value is used for the memory address. P 0 Indicates the use of offset addressing or pre-indexed addressing the W bit determines which . The memory address is generated by applying the offset to the base register value. The