tailieunhanh - Designing with FPGAs and CPLDs- P6

Designing with FPGAs and CPLDs- P6: Designations used by companies to distinguish their products are often claimed as trademarks. In all instances where CMP Books is aware of a trademark claim, the product name appears in initial capital letters, in all capital letters, or in accordance with the vendor’s capitalization preference. Readers should contact the appropriate companies for more complete information on trademarks and trademark registrations. All trademarks and registered trademarks in this book are the property of their respective holders | 134 Chapter 6 Verification Toggle Coverage An older equivalence to code coverage for schematic entry was toggle coverage which specified the percentage of nodes in the design that changed from a 1 to a 0 and from a 0 to a 1 at some time during the simulation. Toggle coverage is not used very much any more now that CPLDs and FPGAs are designed using HDLs rather than schematics. Multilevel Simulation Because you have designed your chip using top-down methodology you can take advantage of the multilevel simulation that can be achieved using HDLs. Your design will be created first using behavioral models that confirm the general algorithms and architecture of the chip. Then behavioral functional blocks can be replaced with RTL descriptions. Finally your design will be synthesized into a gate-level description. The behavioral models will simulate very quickly . use up little computer processing time because by definition behavioral models model only high level functions. Behavioral models shouldn t include clocks and clock edges. As you refine different behavioral blocks into RTL descriptions you can replace those behavioral blocks with their RTL equivalents and resimulate the design. This resimulation with some behavioral blocks and some RTL blocks will take less computer resources and finish much faster than a full RTL simulation. I strongly suggest that the person designing the behavioral block work independently from the person designing the same block in RTL. If the behavioral and RTL code are developed independently when you substitute the RTL block for the behavioral block you will not only test the functionality you will test that the specification from which both blocks were designed is clear and precise. The designer of the behavioral block will make certain assumptions in the design. The RTL designer is unlikely to make those same assumptions unless they are supported by the specification. When the simulation is run on both cases the results won t .