tailieunhanh - Designing with FPGAs and CPLDs- P5

Designing with FPGAs and CPLDs- P5: Designations used by companies to distinguish their products are often claimed as trademarks. In all instances where CMP Books is aware of a trademark claim, the product name appears in initial capital letters, in all capital letters, or in accordance with the vendor’s capitalization preference. Readers should contact the appropriate companies for more complete information on trademarks and trademark registrations. All trademarks and registered trademarks in this book are the property of their respective holders | 104 Chapter 5 Design Techniques Rules and Guidelines Figure Metastability the problem This is where many engineers stop. This metalevel voltage on signal IN though is not really the problem. During the clock cycle the gates driven by signal IN may interpret this metalevel differently. In the figure the upper AND gate G1 sees the level as a logic 1 whereas the lower AND gate G2 sees it as a logic 0. This could occur because the two gates have different input thresholds because of process variations or power voltage variations throughout the die. It is possible that one gate is near the output of FF1 and the other is far away. Such differences in routing can cause the signal to change enough at the input to each gate to be interpreted differently. In normal operation OUT1 and OUT2 should always be the same value. Instead we have created a condition that cannot occur according to the rules of logic. This condition is completely unpredictable. This is the problem with metastability not that an output has a bad voltage but that a single signal is interpreted differently by different pieces of logic. This problem will send the logic into an unexpected unpredictable state from which it may never return. Metastability can permanently lock up your chip. The solution to this metastability problem is shown in Figure . By placing a synchronizer flip-flop S1 in front of the logic the synchronized input SYNC_IN will be sampled by only one device flip-flop FF1 and be interpreted only as a logic 0 or 1. The output of flip-flop FF1 IN will be either a clean 1 or a clean 0 signal. The upper and lower gates G1 and G2 will both sample the same logic level on signal IN. Please purchase PDF Split-Merge on to remove this watermark. Synchronous Design 105 ASYNC_IN CLK D Q S1 SYNC_IN D Q FF1 IN CLK nchronizer Q OUT1 FF2 CLK Q - OUT2 FF3 Figure Metastability the solution1 There is still a very small but nonzero probability that a metastable signal SYNC_IN will