tailieunhanh - Logic kỹ thuật số thử nghiệm và mô phỏng P12

The first 11 chapters of this text focused on manufacturing test. Its purpose is to answer the question, “Was the IC fabricated correctly?” In this, the final chapter, the emphasis shifts to design verification, which attempts to answer the question, “Was the IC designed correctly?” For many years, manufacturing test development and design verification followed parallel paths. Designs were entered via schematics, and then stimuli were created and applied to the design. Design correctness was confirmed manually; the designer applied stimuli and examined simulation response to determine if the circuit responded correctly. Manufacturing correctness was determined by simulating vectors against. | CHAPTER 12 Behavioral Test and Verification INTRODUCTION The first 11 chapters of this text focused on manufacturing test. Its purpose is to answer the question Was the IC fabricated correctly In this the final chapter the emphasis shifts to design verification which attempts to answer the question Was the IC designed correctly For many years manufacturing test development and design verification followed parallel paths. Designs were entered via schematics and then stimuli were created and applied to the design. Design correctness was confirmed manually the designer applied stimuli and examined simulation response to determine if the circuit responded correctly. Manufacturing correctness was determined by simulating vectors against a netlist that was assumed to be correct. These vectors were applied to the fabricated circuit and response of the ICs was compared to response predicted by the simulator. Thoroughness of design verification test suites could be evaluated by means of toggle counts while thoroughness of manufacturing test suites was evaluated by means of fault simulation. In recent years most design starts have grown so large that it is not feasible to use functional vectors for manufacturing test even if they provide high-fault coverage because it usually takes so many vectors to test all the functional corners of the design that the cost of the time spent on the tester becomes prohibitive. DFT techniques are needed both to achieve acceptable fault coverage and to reduce the amount of time spent on the tester. A manufacturing test based on scan targets defects more directly in the structure of the circuit. A downside to this was pointed out in Section that is some defects may best be detected using stimuli that target functionality. While manufacturing test relies increasingly on DFT to achieve high-fault coverage design verification is also changing. Larger more complex designs created by large teams of designers incorporate more functionality