tailieunhanh - Logic kỹ thuật số thử nghiệm và mô phỏng P11

Test strategies described in previous chapters relied on two concepts: controllability and observability (C/O). Good controllability makes it easier to drive a circuit into a desired state, thus making it easier to sensitize a targeted fault. Good observability makes it easier to monitor the effects of a fault. Solutions for solving C/O problems include scan path and various ad-hoc methods. Scan path reduces C/O to a combinational logic problem which, as explained in Chapter 4, is a solved problem (theoretically, at least) | CHAPTER 11 DDQ INTRODUCTION Test strategies described in previous chapters relied on two concepts controllability and observability C O . Good controllability makes it easier to drive a circuit into a desired state thus making it easier to sensitize a targeted fault. Good observability makes it easier to monitor the effects of a fault. Solutions for solving C O problems include scan path and various ad-hoc methods. Scan path reduces C O to a combinational logic problem which as explained in Chapter 4 is a solved problem theoretically at least . 7DDq monitoring is another approach that provides complete observability. Current drain in a properly functioning fully static CMOS IC is negligible when the clock is inactive. However when the IC is defective due to the presence of leakage in the circuit or possibly even to an open current flow usually becomes excessive. This rise in current flow can be detected by monitoring the current supplied by the tester. How effective is this technique for spotting defective ICs In one study it was shown that IDDq testing with a test program that provided 60 coverage of stuck-at faults provided the same AQL as a test program with 90 stuck-at coverage without The stuck-at fault model that we have been dealing with up to this point is not intended to address qualitative issues its primary target is solid defects manifested as signals stuck-at logic 1 or logic 0. An IC may run perfectly well on a tester operating at 1 or 2 MHz at room temperature but fail in the system. Worse still an IC may fail shortly after the product is delivered to the customer. This is often due to leakage paths that degrade to catastrophic failure mode shortly after the product is put into service. BACKGROUND The CMOS circuit was patented in 1963 by Frank His two-transistor inverter consumed just a few nanowatts of standby power whereas equivalent bipolar circuits of the time consumed milliwatts of power in standby mode. During Digital