tailieunhanh - Logic kỹ thuật số thử nghiệm và mô phỏng P8

Chapter 7 focused on methods for integrating design and test activities by capturing verification suites written by logic designers and converting them to test programs. For some ICs, especially those with reasonably high yield, test programs derived from a thorough design verification suite, combined with an IDDQ test (cf. Chapter 11), may produce quality levels that meet or exceed corporate requirements. When it is not possible, or practical, to achieve fault coverage that satisfies acceptable quality levels (AQL) through the use of design verification suites, an alternative is to use an automatic test pattern generator (ATPG). Ideally, one would like. | CHAPTER 8 Design-For-Testability INTRODUCTION Chapter 7 focused on methods for integrating design and test activities by capturing verification suites written by logic designers and converting them to test programs. For some ICs especially those with reasonably high yield test programs derived from a thorough design verification suite combined with an IDDq test cf. Chapter 11 may produce quality levels that meet or exceed corporate requirements. When it is not possible or practical to achieve fault coverage that satisfies acceptable quality levels AQL through the use of design verification suites an alternative is to use an automatic test pattern generator ATPG . Ideally one would like to reach fault coverage goals merely by pushing a button. That however is not consistent with existing state of the art. It was pointed out in Chapter 4 that several ATPG algorithms can in theory at least create a test for any fault in combinational logic for which a test exists. In practice even when a test exists for a large block of combinational logic such as an array multiplier the ATPG may fail to generate a test because of the sheer volume of data that must be manipulated. However the real stumbling block for ATPG has been sequential logic. Because of the inability of ATPGs to successfully deal with sequential logic a growing number of digital designs are being designed in compliance with formal design-for-test-ability DFT rules. The purpose of the rules is to reduce the complexity of the test problem. DFT guidelines prohibit design practices that impede testability and they usually call for the insertion of special constructs into designs solely to facilitate improved testability. The focus over the past two decades has shifted from testing function to testing structure. As an additional benefit testable designs are frequently easier to design and debug. The design restrictions that make it easier to generate test programs also tend to prohibit design practices that .