tailieunhanh - Logic kỹ thuật số thử nghiệm và mô phỏng P5

The previous chapter examined methods for creating sensitized paths in combinational logic extending from stuck-at faults on logic gates to observable outputs. We now attempt to create tests for sequential circuits where the outputs are a function not just of present inputs but of past inputs as well. The objective will be the same: to create a sensitized path from the point where a fault occurs to an observable output. However, there are new factors that must be taken into consideration. A sensitized path must now be propagated not only through logic operators, but also through an entirely new dimension—time | CHAPTER 5 Sequential Logic Test INTRODUCTION The previous chapter examined methods for creating sensitized paths in combinational logic extending from stuck-at faults on logic gates to observable outputs. We now attempt to create tests for sequential circuits where the outputs are a function not just of present inputs but of past inputs as well. The objective will be the same to create a sensitized path from the point where a fault occurs to an observable output. However there are new factors that must be taken into consideration. A sensitized path must now be propagated not only through logic operators but also through an entirely new dimension time. The time dimension may be discrete as in synchronous logic or it may be continuous as in asynchronous logic. The time dimension was ignored when creating tests for faults in combinational logic. It was implicitly assumed that the output response would stabilize before being measured with test equipment and it was generally assumed that each test pattern was independent of its predecessors. As will be seen the effects of time cannot be ignored because this added dimension greatly influences the results of test pattern generation and can complicate by orders of magnitude the problem of creating tests. Assumptions about circuit behavior must be carefully analyzed to determine the circumstances under which they prevail. TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC Two factors complicate the task of creating tests for sequential logic memory and circuit delay. In sequential circuits the signals must not only be logically correct but must also occur in the correct time sequence relative to other signals. The test problem is further complicated by the fact that aberrant behavior can occur in sequential circuits when individual discrete components are all fault-free and conform to their manufacturer s specifications. We first consider problems caused by the presence of memory and then we examine the effects of circuit .