tailieunhanh - A survey of high efficiency context addaptive binary arithmetic coding hardware implementations in high efficiency video coding standard

This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality, low power video applications, addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future. | VNU Journal of Science Comp. Science amp Com. Eng Vol. 35 No. 2 2019 1-22 Original Article A Survey of High-Efficiency Context-Addaptive Binary Arithmetic Coding Hardware Implementations in High-Efficiency Video Coding Standard Dinh-Lam Tran Viet-Huong Pham Hung K. Nguyen Xuan-Tu Tran Key Laboratory for Smart Integrated Systems SISLAB VNU University of Engineering and Technology 144 Xuan Thuy Cau Giay Hanoi Vietnam Received 18 April 2019 Revised 07 July 2019 Accepted 20 August 2019 Abstract High-Efficiency Video Coding HEVC also known as and MPEG-H Part 2 is the newest video coding standard developed to address the increasing demand for higher resolutions and frame rates. In comparison to its predecessor AVC HEVC achieved almost double of compression performance that is capable to process high quality video sequences UHD 4K 8K high frame rates in a wide range of applications. Context-Adaptive Baniray Arithmetic Coding CABAC is the only entropy coding method in HEVC whose principal algorithm is inherited from its predecessor. However several aspects of the method that exploits it in HEVC are different thus HEVC CABAC supports better coding efficiency. Effectively pipeline and parallelism in CABAC hardware architectures are prospective methods in the implementation of high performance CABAC designs. However high data dependence and serial nature of bin-to-bin processing in CABAC algorithm pose many challenges for hardware designers. This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality low power video applications addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future. Keywords HEVC CABAC hardware implementation high throughput power saving. 1. Introduction the ISO IEC produced MPEG-1 and MPEG-4 ITU-T VCEG and ISO IEC-MPEG are the Visual then these two organizations jointly two main dominated international organizations .

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• Hardware implementation
• High throughput
• Power saving
• High efficiency video coding standard
• Coding hardware implementation
• Cryptographic Hardware and Embedded Systems
• The Embedded Systems
• The Cryptographic Hardware
• Modular multiplication in hardware
• XTR Implementation on Reconfigurable Hardware
• Secure the computer
• The Modular Multiplication
• The Software Implementation
• The Hardware Implementation
• Results of the Architectures
• Analysis of the Architectures
• Efficient Hardware Architectures
• A Hardware implementation
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• Discrete fourier transform
• Winograd fourier transform algorithm
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• Transform algorithm for Cryptography
• Parallel Implementation of MAFFT on CUDA Enabled
• CUDA Enabled Graphics Hardware
• Parallel Programming with CUDA
• Multiple Sequence Alignment and MAFFT Algorithm
• Previous Work of Sequence Alignment CUDA
• Profiling of MAFFT
• A HARDWARE ALGORITHM
• HIGH SPEED MORPHEME EXTRACTION
• ITS IMPLEMENTATION
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• A Hardware Architecture
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• Khóa luận tốt nghiệp
• Công nghệ thông tin
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• Future Work and Conclusion
• Residual syntax element
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• CABAC encoder
• Dynamic power consumption
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