tailieunhanh - QUARTUS II INTRODUCTION USING VERILOG DESIGN

Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The Web Edition is a free version of Quartus II that can be downloaded or delivered by mail for free. This edition provided compilation and programming for a limited number of Altera devices. The low-cost Cyclone family of FPGAs is fully supported by this edition, as well as the MAX family of CPLDs, meaning small developers. | VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER ICDREC By NGO DUC HOANG DEPUTY DIRECTOR FEB - 18 - 2007 A TYPICAI FPGA CAD Fl OW M I I I i zrAi rrưM k r LJ ILUW Design Entry Synthesis No Design correct Functional Simulation I Yes Fitting Place and Route Timing Analysis and Simulation No Timing requirements met Yes Programming and Configuration QUARTUS II DEVELOPMENT SYSTEM Fully-integrated Design Tool Multiple Design Entry Methods Logic Synthesis Place and Route Simulation functional and timing Timing and Power Analysis Device Programming and .