tailieunhanh - The method of controlling counter restructure in parallel processing system

This paper proposes the method of controlling counter restructure to meet the requirements of information processing speed. The model used is a restructure controller with FPGA technology. The solution of speed increase is done by maintaining the maximized chain of memory access requests. | Bùi Minh Quý và Đtg Tạp chí KHOA HỌC & CÔNG NGHỆ 93(05): 11 - 15 THE METHOD OF CONTROLLING COUNTER RESTRUCTURE IN PARALLEL PROCESSING SYSTEM Chu Duc Toan* Electric Power University ABSTRACT In parallel processing systems, the efficient use of system resources is an important requirement. Improving performance and increasing speed are related to many issues, both hardware and software [1, 2]. The analysis of processing system operation shows which affects the performance and speed of processing system: During referencing to memory, the processor uses only a command cycle in order to require to read or write data into memory, then wait for the completion of memory cycle before next memory access. Therefore, CPU speed is not taken full advantage; memory access conflicts occur when two or more components simultaneously access to a memory location. This paper proposes the method of controlling counter restructure to meet the requirements of information processing speed. The model used is a restructure controller with FPGA technology. The solution of speed increase is done by maintaining the maximized chain of memory access requests. Keywords: restructure controller with FPGA technology; speed; parallel processing system; performance; the mechanism of parallel memory controller. INTRODUCTION Current processing systems have a big difference between the operation speed of processor and that of memory operations. This rate is generally from 5 to 15 times [4, 5]. To take full advantage of processor time, the memory is organized in parallel as an interleaving model with S-access memory architecture. This is a solution for memory conflicts in accordance with parallel memory models in parallel processing systems. S-access model using lower interleaving address order is described in Figure 1. Saccess method allows all modules to be accessed simultaneously. Each module is Module 0 associated with a data latch. The data from each module is delivered through latch .