tailieunhanh - An efficient 1-D tree architecture of H.264/AVC variable block size motion estimation

An efficient 1-D tree architecture for variable block size motion estimation (VBSME) is proposed in order to reduce the hardware cost and improve the performance. The accumulator in each processing unit is modified to add the sum of absolute differences for every eight cycles. Moreover, the proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of seven modes for VBSME specified in . Our architecture significantly reduces the hardware size by reducing (1) the registers and adders in each processing unit, (2) the comparison elements, and (3) the registers used to store the minimum SADs and motion vectors. | Đàm Minh Tùng và Đtg Tạp chí KHOA HỌC & CÔNG NGHỆ 116 (02): 17 - 22 AN EFFICIENT 1-D TREE ARCHITECTURE OF VARIABLE BLOCK SIZE MOTION ESTIMATION Dam Minh Tung*,Tran Le Thang Dong Center of Electrical Engineering, Duy Tan University, Da Nang SUMMARY An efficient 1-D tree architecture for variable block size motion estimation (VBSME) is proposed in order to reduce the hardware cost and improve the performance. The accumulator in each processing unit is modified to add the sum of absolute differences for every eight cycles. Moreover, the proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of seven modes for VBSME specified in . Our architecture significantly reduces the hardware size by reducing (1) the registers and adders in each processing unit, (2) the comparison elements, and (3) the registers used to store the minimum SADs and motion vectors. The experimental result shows that our proposed architecture reduces the hardware size by while it also increases the operation clock frequency by compared with the best-known architecture. Key words: VBSME, H264/AVC, motion estimation, 1-D tree architecture, VLSI design, FPGA design INTRODUCTION* Block matching algorithm (BMA) is a wellknown method for motion estimation widely used to reduce the temporal redundancy between successive image frames in digital video processing. For previous video compression standards such as MPEG-2, a fixed- size BMA was mostly used. In a typical BMA, each frame of a video sequence is divided into a fixed number of nonoverlapping square blocks. For each block in the current frame, the best matching block is searched in the previous frame under a certain criterion. In most BMAs, the matching criterion used to produce an error cost function is the sum of absolute differences (SADs) between the 16x16 macroblocks (MBs). If x(i,j) and y(i,j) are the pixels of the relevant current and candidate MBs, and m and n are the coordinates of

• Vật lý
• An efficient 1 D tree architecture
• H
• 264 AVC variable block size motion estimation
• Variable block size motion estimation
• The proposed architecture adopts four modes