tailieunhanh - Lecture Introduction to computing systems: Chapter 5 - Yale N. Patt, Sanjay J. Patel

Chapter 5 - The LC-3 instruction set architecture. This chapter presents the following content: ISA overview, operate instructions, data movement instructions, control instructions, LC-3 data path. | Chapter 5 The LC-3 Instruction Set Architecture ISA Overview Operate instructions Data Movement instructions Control Instructions LC-3 data path LC-3 ISA Overview Memory organization Address space: 216 = 64k locations Addressability: Word (= 2 bytes) => total memory = 64k x 2 = 128 kbytes Registers 8 x 16 bit General Purpose Registers: R0 - R7 3 x 1 bit Condition Code Registers: N, Z, P Instructions 16 bit instructions, with 4 bit opcodes Native Data Type: only 2’s complement integer Addressing Modes: Immediate, Register (non-memory addressing modes) Direct, Indirect & Base+Offset (memory addressing modes) 5 - LC-3 Instructions Operate Manipulate data directly ADD, AND, NOT Data Movement Move data between memory and registers LD, LDI, LDR, LEA, ST, STI, STR Control Change the sequence of instruction execution BR, JMP/RET, JSR/JSSR, TRAP, RTI 5 - Instruction Construction Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on. Instruction sets can be complex or simple (CISC, RISC), single-word or multi-word. LC-3 Single word (16 bit) instructions. 4-bit opcode => 16 instructions (very simple set!) remaining 12 bits specify operand(s), according to the addressing mode proper to each instruction. 5 - LC 3 Instructions LC-3 Instruction word: 16 bits Opcode IR[15:12]: 4 bits allow 16 instructions specifies the instruction to be executed Operands IR[11:0]: contains specifications for: Registers: 8 GPRs (. require 3 bits for addressing) Address Generation bits: Offset (11 or 9 or 6 bits) (more later) Immediate value: 5 bits Examples ADD DR, SR1, SR2 ; DR (SR1) + (SR2) [15:12] [11:9] [8:6] [2:0] LDR DR, BaseR, Offset ; DR Mem[BaseR + Offset] [15:12] [11:9] [8:6] [5:0] 5 - Addressing Modes Note: the effective address (ea) is the memory location of the operand The LC-3 supports five addressing modes: the operand is located: in the instruction itself (immediate) in a register in memory: the ea is encoded in . | Chapter 5 The LC-3 Instruction Set Architecture ISA Overview Operate instructions Data Movement instructions Control Instructions LC-3 data path LC-3 ISA Overview Memory organization Address space: 216 = 64k locations Addressability: Word (= 2 bytes) => total memory = 64k x 2 = 128 kbytes Registers 8 x 16 bit General Purpose Registers: R0 - R7 3 x 1 bit Condition Code Registers: N, Z, P Instructions 16 bit instructions, with 4 bit opcodes Native Data Type: only 2’s complement integer Addressing Modes: Immediate, Register (non-memory addressing modes) Direct, Indirect & Base+Offset (memory addressing modes) 5 - LC-3 Instructions Operate Manipulate data directly ADD, AND, NOT Data Movement Move data between memory and registers LD, LDI, LDR, LEA, ST, STI, STR Control Change the sequence of instruction execution BR, JMP/RET, JSR/JSSR, TRAP, RTI 5 - Instruction Construction Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on. .