tailieunhanh - Lecture Operating system concepts (9/ed) - Chapter 8: Main Memory

In this chapter, the following content will be discussed: Background, swapping, contiguous memory allocation, segmentation, paging, structure of the page table, example: The Intel 32 and 64-bit Architectures, example: ARM Architecture. | Chapter 8: Main Memory Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Segmentation Paging Structure of the Page Table Example: The Intel 32 and 64-bit Architectures Example: ARM Architecture Objectives To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging Background Program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are only storage CPU can access directly Memory unit only sees a stream of addresses + read requests, or address + data and write requests Register access in one CPU clock (or less) Main memory can take many cycles, causing a stall Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation | Chapter 8: Main Memory Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Segmentation Paging Structure of the Page Table Example: The Intel 32 and 64-bit Architectures Example: ARM Architecture Objectives To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging Background Program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are only storage CPU can access directly Memory unit only sees a stream of addresses + read requests, or address + data and write requests Register access in one CPU clock (or less) Main memory can take many cycles, causing a stall Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation Base and Limit Registers A pair of base and limit registers define the logical address space CPU must check every memory access generated in user mode to be sure it is between base and limit for that user Hardware Address Protection Address Binding Programs on disk, ready to be brought into memory to execute form an input queue Without support, must be loaded into address 0000 Inconvenient to have first user process physical address always at 0000 How can it not be? Further, addresses represented in different ways at different stages of a program’s life Source code addresses usually symbolic Compiled code addresses bind to relocatable addresses . “14 bytes from beginning of this module” Linker or loader will bind relocatable addresses to absolute addresses . 74014 Each binding maps one address space to another Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages Compile time: If .

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