tailieunhanh - Lecture Digital logic design - Lecture 9: NAND and XOR Implementations

The main contents of the chapter consist of the following: Developing NAND circuits, two-level implementations, multi-level NAND implementations, convert from a network of AND/ORs, exclusive OR, comparison with SOP, parity checking and detecting circuitry. | Lecture 09 NAND and XOR Implementations Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall Overview Developing NAND circuits Two-level implementations Convert from AND/OR to NAND (again!) Multi-level NAND implementations Convert from a network of AND/ORs Exclusive OR Comparison with SOP Parity checking and detecting circuitry Efficient with XOR gates! credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs. Gates A X X = (A + B)’ B AND A X = A • B X or B X = AB 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR A X X = A + B B I A X X = A’ 0 1 1 0 Buffer A X X = A A X 0 0 1 1 NAND A X X = (AB)’ B 0 0 1 0 1 1 1 0 1 1 1 0 NOR 0 0 1 0 1 0 1 0 0 1 1 0 XOR Exclusive OR A X = A B X or B X = A’B + AB’ 0 0 0 0 1 1 1 0 1 1 1 0 A X = (A B)’ X or B X = A’B’+ AB 0 0 1 0 1 0 1 0 0 1 1 1 XNOR Exclusive NOR or Equivalence A B X A B X A X A B X A B X A B X A B X Axioms and Graphical representation of DeMorgan's Law Commutative Law Associative Law Distributive Law Consensus Theorem nand nor and or not Recall that symbolic DeMorgan’s duals exist for all gate primitives The above alternate symbols can be used to . | Lecture 09 NAND and XOR Implementations Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall Overview Developing NAND circuits Two-level implementations Convert from AND/OR to NAND (again!) Multi-level NAND implementations Convert from a network of AND/ORs Exclusive OR Comparison with SOP Parity checking and detecting circuitry Efficient with XOR gates! credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his