tailieunhanh - Lecture VLSI Digital signal processing systems: Chapter 18 - Keshab K. Parhi

Lecture VLSI Digital signal processing systems: Chapter 18 includes the following content: DSP applications, DSP features, addressing modes, standard DSP alternatives, architectural partitioning,. Inviting you refer. | Chapter 18: Programmable DSPs Keshab K. Parhi and Viktor Owall DSP Applications DSP applications are often real time but with a wide variety of sample rates • High rates – Radar – Video • Medium rates – Audio – Speech • Low rates – Weather – Finance Chap. 18 2 .with different demands on • numeric representation – float or fixed – and nmber of bits • Throughput/speed • Power/energy dissipation • Cost Chap. 18 3 DSP features Fast Multiply/Accumulate (MAC) x(n) • FIR D D D • FFT h0 h1 h2 h3 • etc. y(n) • Multiple Access Memories • Specialized addressing modes • Specialized execution control (loops) • Specialized interfaces, . AD/DA Chap. 18 4 Addressing Modes Chap. 18 • Implied addressing P=X*Y; operation sets location • Immediate data AX0=1234 • Memory direct R1=Mem[101] • Register direct sub R1, R2 • Register indirect A0=A0+ *R5 • Register indirect with increment/decrement A0=A0+ *R5++ A0=A0+ .

• Điện - Điện tử
• VLSI Digital signal processing systems
• Digital signal
• Digital signal processing
• DSP systems
• Programmable DSPs
• DSP applications
• FIR Digital Filters
• Parallel processing
• Loop bound
• DSP programs
• Retiming formulation
• Applications of retiming
• Algorithm for unfolding
• Applications of unfolding
• Retiming for folding
• Systolic architecture design
• Projection vector
• Cook toom algorithm
• Fast convolution
• Algorithmic strength reduction
• Parallel FIR filters
• Adaptive filters
• Parallel pecursive
• Round off noise
• State variable description
• Bit level arithmetic architectures
• Parallel multipliers
• Redundant arithmetic
• Redundant number representations
• Numerical strength reduction
• Multiple constant multiplication
• Low power design