tailieunhanh - Lecture VLSI Digital signal processing systems: Chapter 6 - Keshab K. Parhi

Folding is a technique to reduce the silicon area by timemultiplexing many algorithm operations into single functional units (such as adders and multipliers). Chapter 6 will discuss the folding, inviting you refer. | Chapter 6: Folding Keshab K. Parhi • Folding is a technique to reduce the silicon area by timemultiplexing many algorithm operations into single functional units (such as adders and multipliers) • Fig(a) shows a DSP program : y(n) = a(n) + b(n) + c(n) . • Fig(b) shows a folded architecture where 2 additions are folded or time-multiplexed to a single pipelined adder One output sample is produced every 2 clock cycles ⇒ input should be valid for 2 clock cycles. • In general, the data on the input of a folded realization is assumed to be valid for N cycles before changing, where N is the number of algorithm operations executed on a single functional unit in hardware. 2 Folding Transformation : •Nl + u and Nl + v are respectively the time units at which l-th iteration of the nodes U and V are scheduled. • u and v are called folding orders (time partition at which the node is scheduled to be executed) and satisfy 0 ≤ u,v ≤ N-1. • N is the folding factor ., the number of operations folded to a single functional unit. • Hu and Hv are functional units that execute u and v respectively. • Hu is pipelined by Pu stages and its output is available at Nl + u + Pu. • Edge U→V has w(e) delays ⇒ the l-th iteration of U is used by (l + w(e)) th iteration of node V, which is executed at N(l + w(e)) + v. So, the result should be stored for : DF(U→V) = [N(l + w(e)) + v] – [Nl + Pu + u] ⇒ DF(U→V) = Nw(e) - Pu + v – u ( independent of l ) Chap. 6 3 • Folding Set : An ordered set of N operations executed by the same functional unit. The operations are ordered from 0 to N1. Some of the operations may be null. For example, Folding set S1={A1,0,A2} is for folding order N=3. A1 has a folding order of 0 and A2 of 2 and are respectively denoted by (S 1|0) and (S2|2). • Example: Folding a retimed biquad filter by N = 4. Addition time = ., Multiplication time = ., 1 stage pipelined adder and 2 stage pipelined multiplier(., PA=1 and PM=2) The folding sets are S1 = {4, 2, .

• Điện - Điện tử
• VLSI Digital signal processing systems
• Digital signal
• Digital signal processing
• DSP systems
• Retiming for folding
• FIR Digital Filters
• Parallel processing
• Loop bound
• DSP programs
• Retiming formulation
• Applications of retiming
• Algorithm for unfolding
• Applications of unfolding
• Systolic architecture design
• Projection vector
• Cook toom algorithm
• Fast convolution
• Algorithmic strength reduction
• Parallel FIR filters
• Adaptive filters
• Parallel pecursive
• Round off noise
• State variable description
• Bit level arithmetic architectures
• Parallel multipliers
• Redundant arithmetic
• Redundant number representations
• Numerical strength reduction
• Multiple constant multiplication
• Low power design
• Programmable DSPs
• DSP applications