tailieunhanh - A flexible high bandwidth low-latency multi-port memory controller
The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately % of the theoretical bandwidth, and the access latency is minimized as compared to previous designs. | Vietnam Journal of Science and Technology 56 (3) (2018) 357-369 DOI: A FLEXIBLE HIGH-BANDWIDTH LOW-LATENCY MULTI-PORT MEMORY CONTROLLER Xuan-Thuan NGUYEN1, Duc-Hung LE2, *, Trong-Tu BUI2, Huu-Thuan HUYNH2, Cong-Kha PHAM1 1 The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu, 182-8585 Tokyo, Japan University of Science, Vietnam National University – Ho Chi Minh City, 227 Nguyen Van Cu, District 5, Ho Chi Minh City, Viet Nam 2 * Email: ldhung@ Received: 24 January 2018; Accepted for publication: 9 April 2018 Abstract. Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a singleclock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dual-port FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth .
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