tailieunhanh - Lecture Computer organization and assembly language: Chapter 32 - Dr. Safdar Hussain Bouk

After studying this chapter you will be able to understand: Computer system operation, I/O structure, storage structure, storage hierarchy, hardware protection, general system architecture. | CSC 221 Computer Organization and Assembly Language Lecture 32: Intel x86 Instruction Encoding Lecture Outline Encoding Real x86 Instructions x86 Instruction Format Reference x86 Opcode Sizes x86 ADD Instruction Opcode Encoding x86 Instruction Operands, MOD-REG-R/M Byte REG Field of the MOD-REG-R/M Byte MOD R/M Byte and Addressing Modes SIB (Scaled Index Byte) Layout Scaled Indexed Addressing Mode Lecture Outline Encoding ADD Instruction Example Encoding ADD CL, AL Instruction Encoding ADD ECX, EAX Instruction Encoding ADD EDX, DISPLACEMENT Instruction Encoding ADD EDI, [EBX] Instruction Encoding ADD EAX, [ ESI + disp8 ] Instruction Encoding ADD EBX, [ EBP + disp32 ] Instruction Encoding ADD EBP, [ disp32 + EAX*1 ] Instruction Encoding ADD ECX, [ EBX + EDI*4 ] Instruction Encoding ADD Immediate Instruction Encoding Real x86 Instructions It is time to take a look that the actual machine instruction format of the x86 CPU family. They don't call the x86 CPU a Complex Instruction Set Computer (CISC) for nothing! Although more complex instruction encodings exist, no one is going to challenge that the x86 has a complex instruction encoding: Encoding Real x86 Instructions Prefix Bytes 0 to 4 special prefix values that affect the operation of instruction. One or Two byte Instruction opcode (two bytes if the special 0Fh opcode expansion prefix is present) “mod-reg-r/m” byte that spcifies the addressing mode and Instruction operand size. This byte is only required if the instruction supports register or memory operands. Optional Scaled Index Byte if the instruction uses a scaled index memory addressing mode. Displacement. This is 0,1, 2, or 4 byte value that specifies a memory address displacement for the instruction. Imm./Constant data. This is a 0,1, 2, or 4 byte constant value if the instruction has an immediate operand. Encoding Real x86 Instructions Although the diagram seems to imply that instructions can be up to 16 bytes long, in actuality the x86 will not allow . | CSC 221 Computer Organization and Assembly Language Lecture 32: Intel x86 Instruction Encoding Lecture Outline Encoding Real x86 Instructions x86 Instruction Format Reference x86 Opcode Sizes x86 ADD Instruction Opcode Encoding x86 Instruction Operands, MOD-REG-R/M Byte REG Field of the MOD-REG-R/M Byte MOD R/M Byte and Addressing Modes SIB (Scaled Index Byte) Layout Scaled Indexed Addressing Mode Lecture Outline Encoding ADD Instruction Example Encoding ADD CL, AL Instruction Encoding ADD ECX, EAX Instruction Encoding ADD EDX, DISPLACEMENT Instruction Encoding ADD EDI, [EBX] Instruction Encoding ADD EAX, [ ESI + disp8 ] Instruction Encoding ADD EBX, [ EBP + disp32 ] Instruction Encoding ADD EBP, [ disp32 + EAX*1 ] Instruction Encoding ADD ECX, [ EBX + EDI*4 ] Instruction Encoding ADD Immediate Instruction Encoding Real x86 Instructions It is time to take a look that the actual machine instruction format of the x86 CPU family. They don't call the x86 CPU a Complex Instruction Set .