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The Method of Logical Effort

Designing a circuit to achieve the greatest speed or to meet a delay constraint presents a bewildering array of choices. Which of several circuits that produce the same logic function will be fastest? How large should a logic gate’s transistors be to achieve least delay? | The Method of Logical Effort-------1 Designing a circuit to achieve the greatest speed or to meet a delay constraint presents a bewildering array of choices. Which of several circuits that produce the same logic function will be fastest How large should a logic gate s transistors be to achieve least delay And how many stages of logic should be used to obtain least delay Sometimes adding stages to a path reduces its delay The method of logical effort is an easy way to estimate delay in a CMOS circuit. We can select the fastest candidate by comparing delay estimates of different logic structures. The method also specifies the proper number of logic stages on a path and the best transistor sizes for the logic gates. Because the method is easy to use it is ideal for evaluating alternatives in the early stages of a design and provides a good starting point for more intricate optimizations. This chapter describes the method of logical effort and applies it to simple examples. Chapter 2 explores more complex examples. These two chapters together provide all you need to know to apply the method of logical effort to a wide class of circuits. We devote the remainder of this book to derivations that show why the method of logical effort works to some detailed optimization 2 1 The Method of Logical Effort techniques and to the analysis of special circuits such as domino logic and multiplexers. 1.1-----Introduction To set the context of the problems addressed by logical effort we begin by reviewing a simple integrated circuit design flow. We will see that topology selection and gate sizing are key steps of the flow. Without a systematic approach these steps are extremely tedious and time-consuming. Logical effort offers such an approach to these problems. Figure 1.1 shows a simplified chip design flow illustrating the logic circuit and physical design stages. The design starts with a specification typically in textual form defining the functionality and performance targets of .