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Ebook Microelectronic circuit design (4th edition): Part 1

(BQ) Part 1 book "Microelectronic circuit design" has contents: Introduction to electronics, solid state electronics, solid state diodes and diode circuits, field effect transistors, bipolar junction transistors, introduction to digital electronics, complementary mos (cmos) logic design,. and other contents. | 514 Chapter 9 Bipolar Logic Circuits 9.105. The power dissipation of a particular IC chip is limited to 100 W, and the chip will contain 250 million logic gates. The gates must have an average propagation delay of 0.25 ns. (a) What is the powerdelay product of the logic family? (b) What is the lowest PDP that can be plotted on the graph in Fig. 9.51? 9.106. A low-power ECL gate has a 0.5-pJ PDP. (a) What will be the gate delay for a gate operating at a power level of 0.3 mW? (b) What power is required for the gate to achieve a delay of 1 ns? 9.107. The 74LS gate in Fig. 9.51 is redesigned to operate at a power of 5 mW. (a) What is the gate delay of the new design? Assume a constant power-delay product. (b) What power is required to achieve a delay of 0.3 ns? 9.108. The ECL-100K gate in Fig. 9.51 is redesigned to operate at a power of 10 mW. (a) What is the gate delay of the new design? Assume a constant powerdelay product. (b) What power is required to achieve a delay of 0.2 ns? 9.109. CML with a PDP of 25 fJ is to be used in a chip design that requires 50,000 gates. The chip will be placed in a package that can safely dissipate 20 W. What is the minimum logic gate delay that can be used in the design if all the gates operate at the same speed? 9.16 BiCMOS Logic 9.110. (a) Simulate the VTC for the BiNMOS buffer in Fig. 9.58 if the W/L ratios of all the transistors are 10/1. (b) Use SPICE to find the propagation delays for C = 2 pF. Use the BJT parameters from the simulation for Fig. 9.23. 9.111. Add MOS transistors to the circuit in Fig. 9.57 to create a two-input BiCMOS NAND gate. 9.112. Add MOS transistors to the circuit in Fig. 9.58 to create a two-input BiCMOS NAND gate. 9.113. (a) Simulate the VTC for the BiCMOS NOR gate in Fig. 9.60 if the W/L ratios of the NMOS transistors are 4/1 and those of the PMOS transistors are 10/1. (b) Use SPICE fo find the propagation delays for C = 2 pF. Use the BJT parameters from the simulation for Fig. 9.23. PART .